Reliability-Aware Device Design
Investigating trap-assisted tunneling, hot-carrier effects, and BTI in advanced CMOS and TFET devices for robust circuit performance.
ReliabilityTATBTI
Available for research collaboration
Hi, I'mVanshika Ghai
PhD Researcher | VLSI | Semiconductor Devices | TCAD Simulation
4+
Publications
3
Institutions
5+
Projects
PhD @ IIT Bhubaneswar
About Me
Researcher, Engineer, Educator
I'm a PhD Scholar at IIT Bhubaneswar working in Semiconductor Device Modeling and Simulation, with a focus on circuit–device co-optimization using TCAD.
My research explores reliability-aware device design, self-heating effects, stress engineering, and advanced CMOS technologies — bridging device physics with practical circuit-level implications.
Device PhysicsVLSITCADReliabilitySelf-Heating EffectsProcess Simulation
Focus
TCAD, Device–Circuit Co-optimization
Publications
4 peer-reviewed papers
Teaching
TA at IIT BBS & NIT Raipur
Education
Academic Journey
2025 — Present
Doctor of Philosophy (PhD)
Indian Institute of Technology, Bhubaneswar
Semiconductor Device Modeling & Simulation — Circuit-Device Co-optimization using TCAD.
2023 — 2025
M.Tech in VLSI Design & Embedded Systems
National Institute of Technology, Raipur
CPI: 9.08 / 10
2019 — 2023
B.Tech in Electronics & Telecommunication
Bhilai Institute of Technology, Durg
CPI: 9.0 / 10
Research
Areas & Experience
Focus areas within semiconductor device modeling and TCAD simulation.
Self-Heating & Thermal Effects
Studying self-heating in nanoscale FinFETs and vertical TFETs via electro-thermal TCAD simulations for accurate lifetime prediction.
Self-HeatingElectro-ThermalFinFET
Stress Engineering & Advanced CMOS
Exploring strain-engineered SiGe channels and workfunction modulation to enhance switching current ratio and subthreshold swing.
StressSiGeCMOS
TFET-Based Biosensors
Designing charge-plasma hetero Z-shaped TFETs for label-free biosensing with high sensitivity and low power operation.
BiosensorTFETCharge Plasma
Skills
Technical Toolkit
Programming
VerilogSystemVerilogUVMVHDLCC++JavaJavaScript
TCAD Tools
Sentaurus TCADSilvaco TCAD
Simulation
LTspiceHSPICEPSpiceMATLABCadence Virtuoso
Semiconductor Physics
Device PhysicsReliabilitySelf-HeatingProcess SimulationQuantum Tunneling
Software
Xilinx VivadoXilinx ISEGitLinuxLaTeX
Publications
Selected Research Papers
2025Microelectronics Reliability
Reliability assessment of graphene channel vertical TFET: Role of trap-assisted tunneling
Ghai, V.; Dash, S.; Mishra, G.
2025Sensing and Imaging
A Virtually Doped Hetero Z-Shaped Charge Plasma TFET Based Label Free Biosensor
Singh, R.; Ghai, V.; Naugarhiya, A.; Mishra, G.
2025IEEE DevIC 2025
Enhancement of switching current ratio with workfunction modulated SiGe Vertical TFET
Vaishnaw, A.; Jaiswal, A.; Bhange, G.; Ghai, V.; Mishra, G.
2024IEEE EDKCON 2024
Double Gate Tunnel FET with Core-Gate Engineering: An Effective Approach to Suppress Ambipolarity
Sharma, M.; Ghai, V.; Dash, S.; Mishra, G.
Projects
Selected Work
Certifications
Continuous Learning
Sentaurus TCAD Workflow
Synopsys Training
Cadence Virtuoso — Analog Design
Cadence Academic
VLSI Design & Verification
NPTEL
System Verilog & UVM
Coursera
Semiconductor Device Physics
NPTEL
MATLAB for Engineers
MathWorks
Achievements
Milestones
2025
Trainer — KARYASHALA High-End Workshop
Delivered 'Exploring Semiconductor Devices: A Practical Approach to VLSI' at NIT Raipur, organized in association with SERB, Government of India.
2024 — Present
Teaching Assistant
Conducted Verilog and Cadence labs at NIT Raipur and Introduction to Electronics / VLSI Design labs at IIT Bhubaneswar.
2025
Journal Publication — Microelectronics Reliability
Lead author on reliability assessment of graphene-channel vertical TFETs (Elsevier).
2023
M.Tech Admission at NIT Raipur
Joined VLSI Design & Embedded Systems program; graduated with CPI 9.08.
Contact
Let's Connect
Open to research collaborations, talks, and opportunities in device modeling & VLSI.